Qualcomm Unveils HBC Architecture for AI Accelerators with 6x Energy Efficiency

Qualcomm officially unveiled its High-Bandwidth Compute (HBC) architecture, engineered to overcome the 'memory wall' bottleneck—a critical limitation in AI workloads where computational power outpaces memory bandwidth, reducing neural network efficiency. The solution separates the AI accelerator from the SoC, placing the compute module directly beneath the LPDDR memory stack.

This approach leverages through-silicon vias to maximize bandwidth and capacity without relying on expensive HBM memory or complex packaging methods. According to Qualcomm, HBC achieves six times higher bandwidth-per-watt than HBM and over 200 times greater capacity compared to on-chip SRAM. The result is reduced power consumption, lower thermal output, and the elimination of costly interconnects typical of HBM solutions.

Alongside the HBC architecture, Qualcomm announced a roadmap for its AI accelerators. The first, AI200, is slated for late 2024 and will use LPDDR5X memory, offering up to 43 TB of RAM per rack. The next generation, AI250, will feature the first HBC version with an 18x bandwidth increase over AI200. The lineup concludes with AI350, doubling performance via the second HBC iteration. The company emphasizes that this technology enables scalable performance without significant cost escalation.

While other vendors have attempted memory-logic integration—such as GUC’s DRAM-on-Logic (DoL), which delivers up to 5 TB/s bandwidth without HBM3E—Qualcomm has not disclosed specific HBC technical details, complicating direct comparisons. It remains unclear which AI tasks the new accelerators will target, ranging from specialized transformers to universal tensor cores.