SK hynix and TetraMem Unveil Experimental Chip for Energy-Efficient Edge AI

SK hynix and TetraMem, in collaboration with researchers from the University of Southern California, have introduced an experimental memristor-based chip for edge AI devices. The solution leverages in-memory computing (IMC) technology, enabling computations directly within the memory array to reduce energy consumption and accelerate neural network processing.

The chip features 10 neuro-processing units (NPUs), one of which is optimized for depthwise convolution (DWC)—a critical operation in lightweight models like MobileNet. The remaining nine NPUs handle pointwise and dense operations. To enhance DWC efficiency, the block employs a zigzag array topology, enabling parallel execution of 28 independent 3×3 convolutions.

In tests, the chip demonstrated energy efficiency of up to 21.3 TOPS/W at 100 MHz, outperforming Nvidia’s A100 in INT8 mode by an order of magnitude. However, its real-world performance remains uncertain: its peak output of 2.54 TOPS is 16 times lower than Microsoft Copilot+ requirements, and not all NPUs were utilized in experiments. Additionally, memristor precision is limited to 2 bits, compensated by a dual-channel architecture.

The development highlights the potential of memristor technologies for edge AI but requires further research to achieve competitive performance. The chip was manufactured using an outdated 65-nm process, which also impacts its prospects.